Vias are used in semiconductor manufacturing to connect one level of metallization to an underlying level of metallization. Separating the layers of metal is typically an interlayer dielectric (ILD) which is typically formed of silicon dioxide. In forming a via, an anisotropic etch is performed through the ILD layer to expose an area of the underlying metal. In forming the vias through an ILD layer, the ILD thickness varies considerably across individual wafers and from wafer to wafer and lot to lot. Accordingly, to expose the underlying metallization layer, everywhere, most semiconductor manufacturers perform an overetch of the ILD layer. In other words, the etch of the ILD layer is performed longer than would be required for certain thickness, in an effort to remove the thickest portions of the ILD layer.
FIG. 1 illustrates a portion of a semiconductor device 10 which illustrates the problems associated with over etching the ILD layer. Within device 10 is an underlying metallization layer 12 , which is typically in the form of aluminum or an aluminum alloy. Deposited on top of the aluminum layer is a titanium (Ti) layer 14 and a titanium nitride (TiN) layer 16. Titanium nitride layer 16 serves as an anti-reflective coating (ARC) to aid in the photo lithography process, as is conventionally known. Titanium layer 14 serves as a barrier layer, and lowers the contact resistant in a via which is made to underlying metallization layer 12. Over the metallization stack is formed an ILD layer 18. In a preferred embodiment ILD layer 18 is plasma deposited silicon dioxide. As shown, ILD layer 18 has a planar top surface as a result of chemical mechanical polishing (CMP), as is well known in the prior art. After polishing back ILD layer 18, semiconductor device 10 is patterned and etched to form a via 20 through the ILD layer. In one prior art method, via 20 is formed using a chemistry of CHF.sub.3 and argon either with or without CF.sub.4. With such a chemistry, the ratio of the etch rates between ILD layer 18 and titanium nitride layer 16 is approximately between 10:1 and 15:1. However, such etch rate selectivity is insufficient given that ILD layer 18 can vary in thickness from about 70-80% (i.e. 10,000 angstroms (.ANG.) to 17,000 .ANG.). With such a variation in ILD thickness and such etch rate selectivity, it is impossible to guarantee that the via etch stops somewhere between TiN layer 16 and Ti layer 14. It is very important that the via etch stops between these layers, for exposure of the underlying metallization layer 12, typically in the form of aluminum, is detrimental to subsequent plug formation within via 20. More particularly, conventional practices are to deposit a TiN glue layer within via 20. When aluminum is exposed at the bottom of via 20, nitrogen will react with the aluminum to form aluminum nitride which is undesirable because it will increase the resistance of the contact. Lining via 20 with titanium prior to depositing titanium nitride may prohibit the formation of aluminum nitride. However, any exposed titanium will undesirably react with WF.sub.6, a chemical commonly used to form tungsten plugs within via 20.
One method to assure that the via etch stops before exposing the underlying aluminum metallization is to use an etch chemistry which is highly selective to titanium nitride. A few chemistries have been proposed, for example helium has been added to the conventional CHF.sub.3 and argon etch process to improve etch selectivity to about 21:1. However, this too is insufficient given the varying thickness of ILD layer 18 across the wafer and from wafer to wafer and lot to lot. Other selective chemistries are C.sub.4 F.sub.8 or C.sub.3 F.sub.8 based chemistries which are more selective to TiN. However, use of these chemistries suffers from the disadvantage that throughput of wafers is relatively low. For example, a typical etch time using these chemistries is 10 minutes per wafer while using a CHF.sub.3 base chemistries is on the order of 4 minutes per wafer. Furthermore, use of C.sub.4 F.sub.8 and C.sub.3 F.sub.8 based chemistries are less reliable processes. In some instances, the etching of ILD layer 18 will stop without having cleared the underlying metallization due to uncontrolled polymer deposition.
Therefore, there is a need for a new process to be able to etch vias within semiconductor devices without exposing the underlying aluminum metallization, while clearing the ILD layer in the vias despite variations in the ILD thickness. Furthermore, it is desirable that such a process is performed without degrading wafer throughput in the factory.